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    • 专利摘要:
    SUMMARY OF THE INVENTION The present invention provides a method for removing a catalytic element from a crystallized silicon film obtained by solid phase growth using a catalyst element that promotes crystallization, and selectively phosphorus is injected into the crystalline silicon film containing the catalytic element to form phosphorus. When a portion of the injected silicon film is amorphous, a thermal annealing is performed and the silicon film is heated, the catalyst element moves to the amorphous portion into which phosphorus having a large gettering capacity is injected, whereby the catalyst element concentration in the silicon film is lowered, By using such a silicon film, a semiconductor device is manufactured.
    公开号:KR19980070734A
    申请号:KR1019980001975
    申请日:1998-01-23
    公开日:1998-10-26
    发明作者:야마자끼순페이；오누마히데토；다카노다마에；오타니히사시
    申请人:야마자끼순페이；한도타이에네루기겐큐쇼(주)；
    IPC主号:
    专利说明:

    Semiconductor device manufacturing method
    The present invention relates to a method for producing a crystalline silicon semiconductor film such as a polycrystalline silicon film, a single crystal silicon film or a microcrystalline silicon film. The crystalline silicon film manufactured by using this invention is used for various semiconductor devices.
    Thin film transistors (hereinafter referred to as TFTs) using thin film semiconductors are known. The TFT is formed by forming a thin film semiconductor, particularly a silicon semiconductor film, on the substrate and using the thin film semiconductor. Although TFTs are used in various integrated circuits, they are particularly drawing attention as switch elements provided in each pixel of an active matrix liquid crystal display device and driver elements formed in the peripheral circuit portion thereof. In addition, attention has also been paid to an essential technology for multilayer structure integrated circuits (three-dimensional IC).
    Although it is easy to use an amorphous silicon film for the silicon film used for the TFT, there has been a problem that its electrical characteristics are lower than that of the single crystal semiconductor film used in the semiconductor integrated circuit. Thus, TFTs have been used only for limited applications, such as switching elements in active matrix circuits. A crystalline silicon thin film can be used to promote the performance improvement of the TFT.
    Crystalline silicon thin films are referred to as polycrystalline silicon films and silicon films other than polysilicon films, microcrystalline silicon films or monocrystalline silicon films. In order to provide such a silicon film having crystallinity, an amorphous silicon film is first formed, and then the film is crystallized by heating (heat annealing) the film. Such a treatment is referred to as a solid phase growth treatment because the amorphous state is converted into a crystalline state while maintaining the solid state.
    However, in this solid phase growth of silicon, a heating temperature of 600 ° C. or more and a time of 10 hours or more are required, making it difficult to use an inexpensive glass substrate as a substrate. For example, the Corning 7059 glass used in the active liquid crystal display has a strain point of 539 ° C. and has a problem in performing thermal annealing at 600 ° C. or higher in consideration of the large area configuration of the substrate. .
    According to the research conducted by the present inventors in the above problem, any kind of metal element such as nickel is deposited on the surface of the trace amount of the amorphous silicon film, and then heated to crystallize at 550 ° C. for about 4 hours of treatment time. Is performed. A silicon film having naturally excellent crystallinity can be provided by carrying out an annealing treatment at 600 ° C. for 4 hours (see Japanese Patent Application No. JP-A-6-244103).
    In order to introduce the said trace metal element, the method of depositing the catalyst element or the film of the compound by sputtering method (Japanese Patent Application No. JP-A-6-244104), and by spin coating Method of forming a metal element or a compound thereof (Japanese Patent Application No. JP-A-7-130652), a method of forming a film by decomposing a gas containing a metal element by thermal decomposition, plasma decomposition or the like (Japanese Patent Application No. JP-A-7-3355487) and the like can be used according to the respective features.
    Furthermore, a metal element can be selectively introduced into a specific portion, and crystal growth can be extended from the portion where the metal element is enclosed by heating (lateral growth treatment or horizontal growth treatment). The crystalline silicon provided by this method has a directionality of crystallization, and accordingly, very good properties are exhibited according to this directionality.
    Moreover, it is effective to further improve the formation by irradiating a strong beam such as a laser beam after the crystallization step using a metal element (Japanese Patent Application No. JP-A-7-307286). Moreover, it is effective to carry out thermal oxidation following the above-described side growth treatment (Japanese Patent Application No. JP-A-7-66425).
    In this method, when crystallization is performed by using a metal element, a crystalline silicon film having excellent quality is provided at a lower temperature in a shorter time. Although the temperature of the heat treatment strongly depends on various kinds of amorphous silicon films, 450 ° C to 650 ° C is preferred, and more preferably a range of 550 ° C to 650 ° C.
    However, the most serious problem with this method is the removal of metal elements. It cannot be ignored that the metal element introduced into the silicon film adversely affects electrical properties and reliability. In particular, in the step of crystallization using a metal element as the mechanism of the step, the metal element remains in the film as a conductive nitride mainly constituting a serious defect element.
    It is known that generally known metal elements (particularly nickel, palladium, platinum, copper, silver or gold) can be removed by heat treatment in the environment of hydrogen chloride at high temperatures. However, high temperature treatment at 1000 ° C. is required, which is contrary to the idea of low temperature treatment using this metal element. SUMMARY OF THE INVENTION The present invention has been carried out in view of the above problems, and it is an object of the present invention to provide an effective method for removing metal elements by providing gettering with desirable conditions.
    1A-1F show several steps of the first embodiment.
    2A-2G show various steps of the second embodiment.
    3A to 3E show TFT manufacturing steps in the second embodiment.
    4A to 4E show steps of manufacturing a bottom gate type TFT.
    5A to 5E show a bottom gate type TFT fabrication step.
    6A-6F show an overview of an apparatus manufactured using the present invention.
    Fig. 7A is a photograph showing a silicon thin film gettered with nickel element.
    Fig. 7B is a photograph showing a silicon thin film in which no nickel element is gettered.
    8A to 8F show the steps of forming a P-channel type TFT and an N-channel type TFT on the same substrate.
    9A to 9C show the steps of forming a P-channel type TFT and an N-channel type TFT on the same substrate.
    10A to 10F show various steps of the seventh embodiment.
    11A to 11B show TFT characteristics.
    12 is a diagram showing a schematic configuration of a liquid crystal display device.
    * Description of the symbols for the main parts of the drawings *
    11: glass substrate 12: amorphous silicon film
    13: nickel acetate film 14: crystalline silicon film
    15 silicon nitride film 16: mask for injecting phosphorus
    17: region implanted with phosphorus 18: silicon film under the mask
    19: active layer 21: glass substrate
    According to the present invention disclosed herein, a region implanted with a group 15 element (typically phosphorus) at a high concentration is preferentially provided to the silicon film adjacent to the region for first removing the metal element.
    This area is damaged by the implantation of elements of group 15. Furthermore, by performing the heat treatment, the metal element for promoting crystallization is moved to the region in which the elements of group 15 are accelerated and injected.
    For the region in which the elements of group 15 are accelerated,
    (1) a pair of high-density junctions are formed by ion implantation,
    (2) The elements of group 15 themselves provide the property of bonding to metal elements (in particular, these properties are significant in phosphorus).
    Therefore, the movement of the metal element due to the heat treatment in the region implanted with the element of group 15 as described above cannot be reversed.
    Thus, a result is provided in which a metal element for promoting crystallization is moved from the region in which the elements of Group 15 are implanted to the region in which the elements of Group 15 are not implanted by performing heat treatment.
    In particular, when phosphorus is used, the above operation can be remarkably obtained because phosphorus and nickel constitute a stable bonding state at a temperature around 600 ° C.
    Phosphorus and nickel are provided with a number of bonding states such as Ni 3 P, Ni 5 P 2 , Ni 2 P, Ni 3 P 2 , Ni 2 P 3 , NiP 2 , NiP 3 .
    Thus, when nickel is applied as a metal element to promote crystallization and phosphorus is applied as an element of group 15, nickel can be more effectively drawn as a combination with phosphorus. That is, gettering can be performed effectively.
    7A and 7B show the effect of gettering. The photograph shown in Fig. 7A shows a pattern of a silicon film obtained by gettering with a crystalline silicon film obtained by using nickel according to the first configuration of the present invention.
    In the state shown in Fig. 7A, nickel is absorbed into an area outside the pattern (controlled area in the photograph).
    Fig. 7B shows the pattern of the silicon film when no gettering of nickel was performed. The spots observed in the pattern of the silicon film shown in Fig. 7B are minute openings showing a state in which the remaining nickel and nickel compounds are removed. This state is obtained by carrying out a treatment with a special etchant (a mixture of hydrofluoric acid and hydrogen peroxide and water) in which nickel and nickel compounds can be removed with high selectivity.
    Although the treatment using the etchant described above is performed for the pattern shown in Fig. 7A, no spots shown in Fig. 7B are observed because nickel is removed by gettering and no nickel compound appears in the pattern.
    11A shows the characteristics of the TFT manufactured using the film corresponding to FIG. 7A, and FIG. 11B shows the characteristics of the TFT manufactured using the film corresponding to FIG. 7B. Moreover, no treatment of etchant to remove nickel is performed.
    As shown in Figs. 11A and 11B, when nickel remains in the active layer, the OFF characteristic is significantly degraded. Moreover, although representative features are shown in Figs. 11A and 11B, the dispersion of the properties itself is remarkably large when the film shown in Fig. 7B is used.
    The first configuration of the present invention disclosed herein,
    Forming a crystalline film by crystallizing an amorphous silicon film or an amorphous film containing silicon with a metal that promotes the formation of silicon;
    Accumulating stress and strain by irradiating the crystalline film with a pulsed laser beam or equivalent strong beam;
    Selectively forming a mask on the crystalline film;
    Adding an element selected from Group 15 to the crystalline film using the mask;
    A method of masking a semiconductor device is provided, comprising performing heat treatment and gettering the metal from a region where no element is added to a region where the element is implanted.
    The second configuration according to the present invention,
    Forming a crystalline film by crystallizing the amorphous silicon film or the amorphous film including silicon with a metal that promotes crystallization of silicon;
    Selectively forming a mask on the crystalline film;
    Irradiating the crystalline film with a pulsed laser beam or an equivalent strong beam to accumulate stress and strain in areas other than the masked area;
    Accelerating and injecting an element selected from Group 15 into the crystalline film using the mask and damaging the region implanted with the element;
    A method of masking a semiconductor device is provided, the method comprising performing a heat treatment and gettering a metal from a region where an element is not added to a region where an element is added.
    An amorphous silicon film is generally used as an amorphous film. However, compounds of silicon and other elements such as compound semiconductors with Si x Ge 1-x (0x1) can be used. Furthermore, an impurity-added coating may be used to control the coating quality and to control the electrical properties of the device. For example, an amorphous silicon film or the like having a conductivity type can be used.
    As the metal element, a single or multiple kinds of elements selected from the group consisting of Fe, Co, Ni, Cu, Ru, Rh, Pd, Os, Ir, Pt, and Au can be used. In particular, it is preferable to use Ni (nickel) from a viewpoint of reproducibility and an effect.
    Moreover, in gettering, grain boundaries in the silicon film become obstacles for removing metal elements. In general, in the silicon film immediately after solid phase growth, the metal element precipitates as a silicide at the grain boundary, and consequently the grain boundary grows, but this silicide is first thermodynamically stabilized (at the grain boundary because the precipitation is thermodynamically stable). In the first part where the metal element is precipitated), the metal element becomes difficult to move to these regions. Moreover, metal elements moved from other parts are captured and fixed.
    On the other hand, when the laser annealing process is performed by irradiating a pulsed laser beam onto the silicon film crystallized by solid phase growth, the remaining amorphous compound is crystallized, and further, the precipitation of metal elements at the grain boundaries is greatly reduced.
    The tendency for the deposition of metallic elements is reduced because the thermodynamic state is accompanied by a steep change when a pulsed laser (especially with a pulse width of less than 1 μm) is irradiated, and the grain boundaries do not progress sufficiently (on the other hand) Crystallization proceeds with respect to the remaining amorphous components).
    The state in which the pulsed laser beam is irradiated may be regarded as a state in which stress and strain are accumulated in the silicon film. In this state, many metal elements are dispersed and present between the lattice of silicon in the silicon film, so that the metal elements are very easy to move. Moreover, since the large grain boundaries that trap metal elements are also small, subsequent gettering can be effectively performed.
    Such operation and effect can be remarkably obtained by irradiation of pulse oscillating light irradiation, preferably of pulse oscillating laser beam, compared to simple light irradiation.
    According to the present invention disclosed herein, it is preferable that the concentration of the group 15 element acceleratedly injected is higher than 1 digit of the metal element for promoting crystallization.
    For example, the concentration is preferably about 5 × 10 19 to 2 × 10 21 atoms / cm 3 or higher.
    Moreover, in view of the entire coating, the total amount of phosphorus element injected is greater than the total amount of nickel element remaining in the coating, more preferably the total amount of phosphorus element injected is more than 10 times larger than the total amount of nickel element remaining in the coating. Is effective.
    Furthermore, in the acceleration and implantation of group 15 elements, elements such as hydrogen, oxygen or carbon may be injected simultaneously at a concentration of 1 × 10 19 to 1 × 10 21 atoms / cm 3.
    It is important to promote the gettering effect to form a pair of junctions at high density in the region where phosphorus is implanted, and the device which prevents the above crystallization becomes useful.
    In the present invention, gettering is performed in the step of forming to partition the active layer of the transistor by etching the silicon film. A portion of the region in which the group 15 element is implanted can be removed entirely, but a portion can be used as part or all of the source or drain of the transistor. When the region is used as part or all of the source or drain of the P-channel transistor, the P-type region can be formed by injecting P-type impurities or N-type impurities in excess of the amount of implanting elements of group 15. .
    (First embodiment)
    In this embodiment, an example of forming a silicon film having crystallinity on a glass substrate will appear. 1A to 1F, a description will be given of the step of introducing the metal element (nickel is used in this embodiment) and forming the active layer section by gettering the metal element after crystallization.
    According to the step shown by this embodiment, nickel element is introduced to the entire surface of the amorphous silicon film, and crystals are grown evenly and collectively on the entire surface.
    First, an amorphous silicon film 12 is formed by plasma CVD (Chemical Vapor Deposition) on a glass substrate 11 on which a silicon oxide film (not shown) having a thickness of 1000 to 5000 kPa, for example, 2000 kPa, is formed by sputtering or plasma CVD. ) Process or LP (Low Pressure) CVD process.
    An example of a glass substrate is a Corning 1737 substrate with a strain point of 667 ° C.
    In this embodiment, the amorphous silicon film 12 is formed to a thickness of 500 kPa by the plasma CVD process. Moreover, a treatment using hydrofluoric acid is performed to remove the strain and the native oxide film.
    Next, an ultra thin film of nickel is formed. In this embodiment, a method using a spin coating process is applied. Detailed conditions are shown in the first embodiment of Japanese Patent Application No. JP-A-7-130652.
    That is, a silicon oxide film (not shown) having a thickness of 10 to 50 kV provides irradiation of ultraviolet light (low pressure mercury lamp) in an oxygen environment for 5 minutes, and 2 ml of acetic acid having a concentration of nickel of 100 ppm (by weight). The nickel solution is dropped on the substrate, and this state is maintained, and spin dry (2000 rpm, 60 seconds) is performed using a spinner. In this way, an ultrathin film 13 of nickel is formed. Since the super thin film of nickel is extremely thin, the film may not be a continuous film, but there is no resulting problem (FIG. 1A).
    Thus, the operation leads to solid phase growth (crystallization). That is, the substrate is heated to a temperature of 550 to 700 ° C., for example 600 ° C., in a nitrogen environment, and left in this state. Nickel acetate thermally decomposes to about 300 ° C. to become nickel, moreover, functions as a metal at 450 ° C. or higher, and crystallization of the amorphous silicon film proceeds. The crystallized silicon film 14 can be provided by leaving for a required time, for example, 4 hours (Fig. 1B).
    Next, laser annealing is performed by irradiating a pulse oscillation type KrF excimer laser (wavelength: 248 mu m). According to this step, a state in which the nickel element is dispersed is obtained.
    ArF excimer laser, XeCl excimer laser, Co 2 laser, YAG laser and the like can be used as the excimer laser. It is particularly desirable to use excimer lasers at short wavelengths and short pulse intervals.
    Moreover, although strong light irradiation using a halogen lamp or a mercury lamp or the like may be used instead, the effect of forming a non-equilibrium state and easily moving the nickel element cannot be expected.
    Next, the silicon oxide film is removed by the treatment using hydrofluoric acid on the surface already formed. Furthermore, a silicon nitride film 12 (thickness: 1000 kPa) is formed on the silicon film by the plasma CVD process.
    Incidentally, the silicon nitride film is easily peeled off because the stress is very strongly dependent on the composition. In order to solve the above problem, the composition (particularly, the concentration of hydrogen) may be changed, or a silicon oxide film having a thickness of 10 to 100 GPa may be formed between the silicon film 14 and the silicon nitride film 15 (Fig. 1c).
    Thereafter, the mask 16 is formed by etching the silicon nitride film 15 using the mask 16.
    Next, phosphorus ions are implanted into the region not covered by the mask by using the mask 16. In this step, plasma doping treatment is used.
    In accordance with the step of doping phosphorus, the acceleration voltage is set to 5 to 25 kV, and the amount of dose is set to 1 × 10 13 to 8 × 10 15 atoms / cm 2, for example, 5 × 10 14 atoms / cm 2.
    In this case, considering that phosphorus is uniformly distributed in the silicon film, the concentration is 1 × 10 20 atoms / cm 3. In this way, a region 17 into which phosphorus is implanted is obtained (FIG. 1D).
    For the step of doping phosphorus, a condition is set at which the concentration becomes 1 digit or more higher than the concentration of nickel in the film.
    According to a preliminary experiment, the concentration of nickel in the crystalline silicon film 14 in the state of FIG. 1B is about 5 x 10 18 atoms / cm -3 on average (the density distribution exists in the thickness direction). Therefore, in this embodiment, the doping conditions are set so that the concentration of phosphorus is about 50 times the nickel concentration.
    Thereafter, thermal annealing is performed at 600 ° C. for 2 hours in a nitrogen environment to heat the silicon film 14. By this step, the metal element present in the silicon film region 18 under the mask (which is intrinsic) is immutably moved to the region 17 into which phosphorus is injected. That is, the metal element present in the silicon film region 18 under the mask is gettered to the region in which phosphorus is implanted (Fig. 1E).
    The heating temperature in this gettering step is preferably selected from a temperature range of 500 to 700 ° C, particularly preferably of a temperature range of 550 to 650 ° C.
    Next, the region 17 is removed using the mask 16. Next, the mask 16 is removed and a smaller mask than the mask 16 is placed to pattern the area indicated by reference numeral 19 in the figure.
    In this case, the area having the dimension indicated by the symbol X which is part of the gettering area 19 is removed. This is because the nickel element may be attached to the end of the region 18 in which the nickel element removes the region 17, and its relation needs to be excluded (FIG. 1F).
    In this way, the active layer 19 of the thin film transistor is obtained. This active layer 19 comprises a crystalline silicon film with high crystalline performance, where the concentration of nickel element is reduced. Thereafter, a thin film transistor is manufactured by using a region as an active layer.
    (Second embodiment)
    This embodiment relates to a configuration in which a metal element is selectively introduced into an amorphous silicon film, and solid phase growth referred to as lateral growth in a direction parallel to the substrate is performed from a region where the metal element is introduced into another region.
    2A-2G show an overview of the manufacturing steps according to this embodiment.
    First, an amorphous silicon film 22 is formed on a glass substrate on which a silicon oxide film (not shown) having a thickness of 1000 kPa to 5000 kPa is formed by a plasma CVD process or a low pressure CVD process to a thickness of 500 kPa to 1000 kPa.
    Next, the silicon oxide film 23 constituting the mask film is formed by a plasma CVD process to a thickness of 1000 mW or more, here 1200 mW. As to the thickness of the silicon oxide film 23, it was confirmed that there is no problem in forming a film having a thickness of 500 mV according to an experiment conducted by the present inventors and the like. Further clearance is provided to prevent the introduction of nickel in the portion (Fig. 2A).
    Moreover, the silicon oxide film 23 is etched in an essential pattern by general photolithography patterning to form a window 24 for introducing nickel (FIG. 2B).
    Similar to the first embodiment, an ultra thin film 25 having a desired thickness is deposited by spin coating on the substrate on which the fabrication is performed (Fig. 2C).
    As a method of introducing a metal element, in addition to the above-described treatment using dissolution, CVD treatment, plasma treatment (discharge treatment using an electrode containing the metal), ion implantation treatment, gas adsorption treatment, and the like can be used.
    Subsequently, by performing heat treatment at 600 ° C. (nitrogen environment) for 8 hours, the amorphous silicon film 22 is crystallized. In this case, first, crystallization starts at the portion 26 where the nickel acetate film is in close contact with the amorphous silicon film. Thereafter, crystallization proceeds around it, and crystallization is also performed in the region 27 covered with the mask film 23 (FIG. 2D).
    When crystallization in the transverse direction (crystal growth in the direction parallel to the substrate) is performed as shown in Fig. 2D, three regions with different properties are provided in a large classification.
    The first region is a region where the nickel film is adhered to the amorphous silicon film, which is indicated by reference numeral 26 in FIG. 2D. This region is crystallized at the initial stage of the thermal annealing step. This area is called the vertical growth area. In this region, the concentration of nickel is relatively high, the direction of crystallization is not aligned, and as a result, the crystallization performance of silicon is not so excellent, so the etching ratio to the hydrofluoric acid or other acid is relatively large.
    The second region is a region where crystallization is performed in the transverse direction, which is indicated by reference numeral 27 in FIG. 2D. This area is called the lateral growth area. In this region, the direction of crystallization is aligned, and the concentration of nickel is relatively low, and this region is a preferable region for use in the apparatus.
    The third region is an amorphous region in which no crystallization in the transverse direction has been reached.
    Next, the silicon oxide mask 23 is further etched (patterned), and then the mask 28 is formed. In this case, when wet etching is applied to etching the silicon oxide mask 23, the silicon film 26 in the opening 24 can be strongly etched depending on the etchant.
    This is because the concentration of nickel in that portion is high. This is preferable in view of partially blocking nickel from the silicon film, but may affect the underlying film or the substrate. If the latter does not cause various problems, a step of practically etching nickel may be applied (in this case, mainly nickel is in the form of a nickel silicon compound).
    Next, phosphorus ions are implanted by the ion doping process into the region not covered by the mask using the mask 28. Hydrogen phosphide (PH 3 ) diluted to 5% with hydrogen is used for the doping gas, the acceleration voltage is set to 10 kV, and the dose amount is set to 8 x 10 14 atoms / cm 2. If it is determined that phosphorus is uniformly distributed in the silicon film, the concentration is 2 x 10 20 atoms / cm 3. In this way, a region 29 into which phosphorus has been implanted is provided (Fig. 2E).
    Moreover, the thermal annealing treatment was performed at 600 ° C. for 2 hours in a nitrogen environment, so that the metal element present in the silicon film region 30 under the mask was gettered to the region 29 into which phosphorus was implanted (FIG. 2F).
    Next, the mask 28 is removed, and a portion of the silicon film 27 (including the phosphorus-implanted region 29) is etched to form an active region 31 of the transistor (FIG. 2G).
    By the above steps, an active layer 31 which is crystallized and has a low concentration of nickel is provided.
    Incidentally, a part of the region implanted with phosphorus forming the division of the active layer may be left, and this region may be used for the TFT.
    This example is described with reference to Figs. 3A to 3E. According to the above example, by using a portion of the phosphorus-implanted region 29 provided for gettering, a source and a drain are formed, and then a low concentration drain region by self-regulated doping using the gate electrode as a mask. Is formed.
    In this way, there is no need to separately prepare a step for doping the high concentration N-type region.
    In the following a detailed description of the above manufacturing steps is given. First, processing is performed in the state shown in Fig. 2F by the steps described with reference to Figs. 2A to 2F. This state is shown in Fig. 3A, and the same reference numerals are given in the same parts as in Fig. 2F. That is, the phosphorus implanted region is 29, the phosphorus implanted mask is 28, and the crystalline silicon film below is 30 at the same time. The gettering treatment of the metal element is completed by the thermal annealing treatment. Moreover, the portion 24 where nickel is selectively implanted is present in a portion of the region where phosphorus is implanted (FIG. 3A).
    Next, the active layer 34 is obtained by using the mask 28. In this case, part of the region in which phosphorus is implanted is left, and the source 32 and the drain 33 of the TFT are formed by that part. That is, the active layer 34 is formed by the source 32 and the drain 33 and the intrinsic region 30 are inserted therebetween. However, the portion 24 into which nickel has been implanted cannot be used as a source and a drain because the chemical properties of the silicon film are unstable (Fig. 3B).
    Thereafter, a silicon oxide film 35 having a thickness of 200 kV to 1500 kV or in this case 1000 kV is deposited by the plasma CVD process. The silicon oxide film functions as a gate insulating film. Next, a polycrystalline silicon film doped with phosphorus having a thickness of 2000 GPa is formed by a low pressure CVD process, and the film is patterned to form a gate electrode 36 (Fig. 3C).
    Incidentally, the gate electrode can be constructed by using various silicon compound materials or aluminum.
    After that, impurities (phosphorus) are injected into the island-like silicon film of the TFT by self-adjusting using the gate electrode 36 as a mask. Hydrogen phosphide (PH 3 ) is used as the doping gas. Since the doping is performed through the gate insulating film, the acceleration voltage is set to 50 to 80 kV. Further, the amount of dose is set to 1 × 10 13 to 4 × 10 14 atoms / cm 2, for example, 5 × 10 13 atoms / cm 3. As a result, the low concentration N-type region 37 is formed. The concentration of phosphorus in the region is estimated to be 1 x 10 19 atoms / cm 3 (Fig. 3D).
    Subsequently, a silicon oxide film is formed to a thickness of 3000 kPa to 8000 kPa by the plasma CVD treatment of oxygen or the reduced pressure CVD treatment or CVD treatment of oxygen using TEOS (tetra ethoxy silane) as the interlayer insulating coating 28 on the entire surface. do. The substrate temperature is set at 250 ° C to 450 ° C, for example 350 ° C. After film formation, the silicon oxide film may be mechanically polished or planarized by an etch back system to provide flatness of the surface.
    Further, by etching the interlayer insulating film 38, contact holes are formed in the source and the drain of the TFT to form the aluminum wiring / electrode 39. Finally, the assembly is annealed at 300 to 400 ° C. for 01 to 2 hours in hydrogen. In this way, the TFT is terminated (Fig. 3E).
    (Third embodiment)
    According to this embodiment, an example of improving the manufacturing steps of the first embodiment will be shown. According to this embodiment, after providing the mask 16 for implanting phosphorus ions, laser annealing is performed. This case is more disadvantageous than the first embodiment in that nickel cannot be dispersed under the mask 16.
    (Example 4)
    In this embodiment, an example of the case where the bottom gate type TFT is manufactured by using the present invention disclosed herein will appear. First, as shown in Fig. 4A, a silicon oxide film 402 is formed on the glass substrate 401 as an underlayer.
    Next, a metal silicon compound constituting the metal silicon compound is formed. Further, a gate insulating film 404 is formed.
    Next, an amorphous silicon film 405 is formed. Furthermore, a mask 400 made of a silicon oxide film is formed. The mask is provided with an opening 40.
    Next, using a nickel acetate solution, a state in which the nickel element is in contact with the surface and held as shown by reference numeral 406 in the figure is obtained (Fig. 4A).
    Next, the amorphous silicon film 405 is crystallized by heating. At this time, crystal growth proceeds in the direction indicated by arrow 41 in the figure.
    In this way, a crystalline silicon film 407 is obtained (Fig. 4B).
    Next, the laser beam is irradiated (FIG. 4C).
    Next, a mask 408 made of a silicon oxide film is formed (FIG. 4D).
    Next, heavy doping of the P (phosphorus) element is performed. In this step, heavy doping of the P element is performed in regions 409 and 411. Moreover, doping is not performed in region 410 (FIG. 4E).
    Next, heat treatment is performed in a mixed environment of HCl, so that the nickel element is gettered as shown in Fig. 5A.
    Thereafter, the mask 408 made of a silicon oxide film is removed, and a resist mask 412 is newly formed (FIG. 5B).
    The silicon film is patterned by using the resist mask 412. Thus, part of the silicon film indicated by reference numeral 413 remains (Fig. 5C).
    Next, a channel protective film 414 is provided, and the doping of the impurity providing one conductivity type is performed using the time channel protective film as a mask. As a result, the source region 415 and the drain region 417 are formed (FIG. 5D).
    Moreover, the laser beam is irradiated and the source and drain regions are activated.
    Next, a silicon nitride film 418 and a polyimide resin film 419 are formed as the interlayer insulating film.
    Further, contact holes are formed, and source electrode 420 and drain electrode 421 are formed. In this way, a reverse staggered thin film transistor is completed as shown in Fig. 5E.
    (Example 5)
    In this embodiment, the outline of the apparatus using the invention disclosed in this specification is shown. 6A-6F show their respective outlines.
    6A shows a portable information processing terminal provided with a communication function using a telephone network.
    This electronic device is provided with an integrated circuit 2006 using a thin film transistor inside the main body 2001. Furthermore, an active matrices type liquid crystal display device 2005, a camera portion 2002 for capturing an image, and an operation switch 2004 are provided.
    12 shows an outline of the configuration of the liquid crystal display device. Each circuit block shown in Fig. 12 is constituted by, for example, a combination of CMOS (Complementary Metal Oxide Semiconductor) circuits made of thin film transistors.
    6B shows an electronic device called a hand mount display. This device has a function of visually displaying an image of the eye's calmness by mounting the main body 2101 on the head by a band 2103. This image is formed by the liquid crystal display device 2102 corresponding to the left and right eyes.
    According to such an electronic device, a circuit using a thin film transistor is utilized for miniaturization and light weight of the device.
    6C is provided with a function for displaying map information or various types of information based on a signal from a satellite. The information from the satellite captured by the antenna 2204 is processed by an electronic circuit provided inside the main body 2201, and the necessary information is displayed on the liquid crystal display 2202.
    The device is operated with an operation switch 2203. Also in such an apparatus, a circuit using a thin film transistor is utilized to miniaturize the whole structure.
    6d shows a portable telephone. This electronic device is provided with a main body 2301, an antenna 2306, an audio output unit 2302, a liquid crystal display device 2304, an operation switch, and an audio tension unit 2303.
    Fig. 6E shows an electronic device, i.e., a portable image capture device called a video camera. This electronic device is provided with a main body 2401, a liquid crystal display 2402 attached to the opening member and the closing member, and an operation switch 2404 attached to the opening member and the closing member.
    Further, the main body 2401 is provided with an image receiving unit 2406, an integrated circuit 2407, an audio input unit 2403, an operation switch 2404, and a battery 2405.
    Fig. 6F shows an electronic device, that is, a projection type liquid crystal display device. This apparatus is provided with a light source 2502, a liquid crystal display device 2503, and an optical system 2504 on the main body 2501, and has a function of projecting an image on the screen 2505.
    Furthermore, in the above-described electronic device, any one of a transmission type device and a reflective type device may be used as the liquid crystal display device. The transmission type device is advantageous in view of display characteristics, and the reflection type device is advantageous in the case of pursuing low power consumption or small size and light weight. In addition, an active matrix EL (Electroluminescence) device, a plasma device, or the like can be used as the display device.
    (Example 6)
    This embodiment shows the basic circuit elements used to construct the various devices shown in Figs. 6A to 6F.
    This embodiment shows a configuration in which a P-channel type TFT (PTFT) and an N-channel type TFT (NTFT) are integrated on the same substrate.
    The general circuit is constructed as a basic element by a CMOS circuit in which PTFT and NTFT are completely configured.
    In this embodiment, an example in which a nickel element is introduced to the entire surface and a technique for crystallizing the entire surface is used.
    8A-8F show the manufacturing steps. First, an amorphous silicon film 802 is formed on the glass substrate 801. Next, the nickel element is held in contact with the surface of the amorphous silicon film 802 indicated by reference numeral 803 using the solution (Fig. 8A).
    Next, a crystalline silicon film 804 is provided by performing a heating operation to crystallize the film (Fig. 8B).
    Next, the nickel element remaining in the film is dispersed by performing laser annealing (Fig. 8C).
    Furthermore, masks 805 and 806 are disposed, and phosphorus ions are implanted. In this way, phosphorus ions are doped into regions 807, 808, and 809 (Fig. 8D).
    Next, an element of nickel is gettered in the region 807 (Fig. 8D).
    Next, the masks 805 and 806 are removed. In this way, regions 810 and 811 of the crystalline silicon film in which nickel is gettered outward are obtained. In this case, the region 810 constitutes an active layer of NTFT (Fig. 8E).
    Next, a gate insulating film 812 is formed, and gate electrodes 813 and 814 made of aluminum are formed. Anodized films denoted by reference numerals 815 and 816 are formed around the gate electrode (Fig. 8F).
    Next, phosphorus is doped into regions 901, 903, 904 by doping phosphorus by a plasma doping process.
    In this step, the undoped regions 902 and 905 constitute the channel region in a later step.
    Next, a mask 907 is provided and boron is doped. In this step, regions 908 and 909 are inverted from N type to P type.
    In this way, the PTFT can be formed on the left side, while the NTFT can be formed on the right side (Fig. 9B).
    Next, a silicon nitride film 910 is formed as an interlayer insulating film, and a polyimide resin film 911 is formed.
    Further, a contact hole is formed, and a source electrode 912 and a drain electrode 913 of the PTFT, a source electrode 915 and a drain electrode 914 of the NTFT are formed. In this way, the configuration shown in Fig. 9C can be provided.
    Here, a CMOS structure can be obtained by connecting the gate electrode of each TFT and connecting each drain electrode.
    (Example 7)
    This embodiment shows an example of improving the manufacturing steps shown in Figs. 2A to 2G, and Figs. 10A to 10F show the manufacturing steps of this embodiment.
    First, the approach to the step shown in Fig. 10D is the same as the step shown in Fig. 2D.
    When the state shown in Fig. 10D is obtained, phosphorus ions are implanted into the region 101 under this state. That is, phosphorus ions are also implanted by using a mask used to selectively introduce nickel element (Fig. 10E).
    Further, by performing the heat treatment shown in Fig. 10F, the nickel element is gettered to the region 101.
    Thereafter, the region 10 is etched and the mask 23 is removed. Moreover, the region 27 crystallized in the required pattern is patterned.
    (Example 8)
    This embodiment shows an example where a gas phase process is used as a method of introducing phosphorus for gettering.
    In this case, description will be given when nickel is used as the metal element for promoting crystallization and phosphorus is used as the element of Group 15.
    According to the present embodiment, a film containing P is deposited on the surface of a region (eg, region 17 in FIG. 1D) for gettering nickel by CVD processing using PH 3 gas.
    In this case, the effect of gettering cannot be provided in the damaged region provided when phosphorus ions are acceleratedly implanted. However, since the gettering effect of phosphorus on nickel is extremely high, nickel cannot gettered as shown in Fig. 1E.
    (Example 9)
    This embodiment shows an example in which a liquid phase process is used as a method of introducing a metal element into a region into which phosphorus is introduced for gettering.
    According to the present exemplary embodiment, Phosphorus Silicate Glass (PSG) is formed in a region for gettering a metal element.
    For example, in the step of FIG. 1D, a PSG film is formed on the region 17, and then heat treatment is performed so that the nickel element can be gettered from the region 18. FIG.
    According to the present invention, by using the metal element to promote the crystallization of the amorphous silicon film, the metal element can be effectively removed by the crystallized silicon film. As a result, a large amount of highly reliable electronic device using a crystalline silicon film can be provided. As mentioned above, the present invention is industrially useful.
    权利要求:
    Claims (22)
    [1" claim-type="Currently amended] In the semiconductor device manufacturing method,
    Forming a crystalline film by crystallizing a semiconductor film made of silicon using a metal that promotes crystallization of the semiconductor film;
    Accumulating stress and strain by irradiating the crystalline film with a pulsed laser beam or an equivalent beam;
    Selectively forming a mask on the crystalline film;
    Using the mask to add an element selected from Group 15 to the crystalline film;
    And performing a heat treatment for gettering the metal from a region where the element is not added to a region where the element is injected.
    [2" claim-type="Currently amended] The method of claim 1, wherein the metal that promotes crystallization is selected from the group consisting of Fe, Co, Ni, Cu, Ru, Rh, Pd, Os, Ir, Pt, and Au.
    [3" claim-type="Currently amended] The method of manufacturing a semiconductor device according to claim 1, wherein phosphorus is used as said element selected from said group 15.
    [4" claim-type="Currently amended] A method according to claim 1, wherein said element is selected from the group consisting of nitrogen, phosphorus, arsenic, antimony and bismuth as said element selected from said group 15.
    [5" claim-type="Currently amended] The semiconductor device manufacturing method according to claim 1, wherein the semiconductor film is formed on a glass substrate having a strain point of 700 ° C or less.
    [6" claim-type="Currently amended] 2. The method of claim 1, wherein said adding step of said element selected from said Group 15 is performed by accelerating and implanting said ionized element to intentionally damage the region into which said element is implanted.
    [7" claim-type="Currently amended] The method of manufacturing a semiconductor device according to claim 1, wherein said adding step of said element selected from said group 15 is performed using a solution containing said element.
    [8" claim-type="Currently amended] The method of manufacturing a semiconductor device according to claim 1, wherein said adding step of said element selected from said Group 15 is performed by a gas phase reaction using a gas containing said element.
    [9" claim-type="Currently amended] The semiconductor device manufacturing method according to claim 1, wherein a material represented by Si x Ge 1-x (0 x 1) is used as the semiconductor film containing silicon.
    [10" claim-type="Currently amended] The method of claim 1, wherein the heat treatment is performed at a temperature selected from a temperature range of 500 ° C. to 700 ° C. 7.
    [11" claim-type="Currently amended] The method of claim 1, wherein the heat treatment is performed at a temperature selected from a temperature range of 550 ° C. to 650 ° C. 7.
    [12" claim-type="Currently amended] In the semiconductor device manufacturing method,
    Forming a crystalline film by crystallizing a semiconductor film containing silicon using a metal that promotes crystallization of the semiconductor film;
    Selectively forming a mask on the crystalline film;
    Accumulating stress and strain in an area where said mask is not formed by irradiating a pulsed laser beam or an equivalent strong beam onto said crystalline film;
    Accelerating and injecting an element selected from Group 15 into the crystalline film using the mask to damage the region into which the element is implanted;
    And performing heat treatment from a region where the element is not implanted to a region where the element is implanted to getter the metal.
    [13" claim-type="Currently amended] 13. The method of claim 12, wherein the metal that promotes crystallization is selected from the group consisting of Fe, Co, Ni, Cu, Ru, Rh, Pd, Os, Ir, Pt, and Au.
    [14" claim-type="Currently amended] 13. A semiconductor device manufacturing method according to claim 12, wherein phosphorus is used as said element selected from said group 15.
    [15" claim-type="Currently amended] The semiconductor device manufacturing method according to claim 12, wherein said element is selected from the group consisting of nitrogen, phosphorus, arsenic, antimony and bismuth as said element selected from said group 15.
    [16" claim-type="Currently amended] The method of manufacturing a semiconductor device according to claim 12, wherein the semiconductor film is formed on a glass substrate having a strain point of 700 ° C or less.
    [17" claim-type="Currently amended] 13. The method of claim 12, wherein the implanting of the element selected from the group 15 ionizes the element, intentionally damaging the region into which the element is implanted.
    [18" claim-type="Currently amended] 13. The method of claim 12, wherein the implanting of the element selected from the group 15 is performed by using a solution containing the element.
    [19" claim-type="Currently amended] The method of manufacturing a semiconductor device according to claim 12, wherein said injecting said element selected from said group 15 is carried out in a gas phase reaction using a gas containing said element.
    [20" claim-type="Currently amended] The semiconductor device manufacturing method according to claim 12, wherein a material represented by Si x Ge 1-x (0x1) is used as the semiconductor film containing silicon.
    [21" claim-type="Currently amended] 13. The method of claim 12, wherein the heat treatment is performed at a temperature selected from a temperature range of 500 [deg.] C to 700 [deg.] C.
    [22" claim-type="Currently amended] 13. The method of claim 12, wherein the heat treatment is performed at a temperature selected from a temperature range of 550 deg. C to 650 deg.
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    同族专利:
    公开号 | 公开日
    JP3942683B2|2007-07-11|
    US7115452B2|2006-10-03|
    KR100572819B1|2006-04-24|
    KR100538892B1|2006-03-20|
    US6162704A|2000-12-19|
    JPH10223533A|1998-08-21|
    US20030087509A1|2003-05-08|
    US6461943B1|2002-10-08|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-02-12|Priority to JP97-044573
    1997-02-12|Priority to JP04457397A
    1998-01-23|Application filed by 야마자끼순페이, 한도타이에네루기겐큐쇼(주)
    1998-10-26|Publication of KR19980070734A
    2006-03-20|Application granted
    2006-03-20|Publication of KR100538892B1
    优先权:
    申请号 | 申请日 | 专利标题
    JP97-044573|1997-02-12|
    JP04457397A|JP3942683B2|1997-02-12|1997-02-12|Semiconductor device manufacturing method|
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